Method for manufacturing a semiconductor device having a dummy section

ABSTRACT

There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of U.S. application Ser. No. 12/458,324,filed on Jul. 8, 2009, and allowed on Oct. 12, 2017, which is based on,and claims priority to, Japanese Patent Application No. 2008-180289,filed on Jul. 10, 2008. The entire disclosures of these prior U.S. andforeign applications are incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a method for manufacturing asemiconductor device and a semiconductor package, and particularlyrelates to a semiconductor device having a Through Silicon VIA electrodestructure.

2. Description of the Related Art

Recent versions of information devices such as digital cameras andmobile phones equipped with a camera function embody considerably higherlevels of miniaturization, density, and functionality. A wafer-levelchip size package (hereinafter referred to as W-CSP) is a knowntechnique for reducing the size of CCD sensors, CMOS sensors, and otherimaging elements used in such devices to fit in a chip-scale package.

The W-CSP is a new concept package in which all the assembly steps arecompleted in a wafer state.

A Through Silicon VIA electrode structure is adopted in the image sensorof a W-CSP structure because reliability can be improved and the devicecan be made smaller. An electrode that allows the semiconductor deviceto have signal interchange with the exterior is ordinarily formed on thesame surface as the formation surface of the semiconductor elements. Incontrast, with Through Silicon VIA electrodes, Through Silicon VIA holesare formed in the thickness direction of the chip from the reverse sideof the chip using microfabrication, conductive wiring is formed insidethe Through Silicon VIA holes, and the conductive wiring is connected tosurface electrodes, whereby signal interchange is made possible from thereverse surface of the chip which is not ordinarily used. Stacking aplurality of chips using a Through Silicon VIA electrode technique andforming signal transmission pathways in the thickness direction of thechip makes it possible to make wiring distances shorter than withconventional wiring. Therefore, packaging density can be dramaticallyimproved and speed and reliability can be increased. Methods formanufacturing CSP having a Through Silicon VIA electrode are describedin, e.g., Japanese Laid-open Patent Application Nos. 2006-128171 and2005-235858.

A CMOS sensor, for example, is an imaging element for reading anelectric charge accumulated in a photodiode that has been converted tovoltage and amplified in each pixel, and is provided with a photodiode,a cell amplifier, and the like inside a unit cell. A CMOS sensor iscomposed of a plurality of active elements that constitute a photodiodeand a cell amplifier on a semiconductor substrate, and STI (shallowtrench isolation) is used for discrete insulation between each activeelement. The region for forming transistors, diodes, and other activeelements on the semiconductor substrate is referred to as an activearea, while a region other than the active area is referred to as anon-active area. In other words, STI and other element isolation regionsbelong to the non-active area. Flattening by CMP (chemical mechanicalpolishing) is carried out in the step for forming an STI on thesemiconductor substrate, and dishing occurs. In dishing, the centerportion of the STI is formed into a concave dish-shape by the differencein polishing rates between the oxide film constituting the STI and thenitride film provided as a stopper during polishing when the surfacearea of the STI region is increased. Difficulties arise in later stepsbecause the flatness of the substrate is detracted when dishing occurs.A technique for preventing dishing involves the formation of a dummypattern having a plurality of island-shaped dummy sections inside thenon-active area, which is the location when dishing occurs. The dummypattern is formed by leaving the base material of the silicon substratein island shapes inside the STI region, and is therefore referred to asa dummy active. Dishing can be prevented because the difference betweenthe polishing rates in the CMP step is lessened by the uniform formationof a dummy active in the non-active area (STI region).

In an image sensor having a W-CSP structure, a Through Silicon VIAelectrode is generally formed in the non-active area in which activeelements are not formed, and a plurality of dummy actives is formed inorder to prevent dishing in the non-active area as described above. Inother words, a dry etching step for forming Through Silicon VIA holes inthe non-active area in which the plurality of dummy actives is formed isincluded in the steps for manufacturing an image sensor. However, thereis a problem in that notches (outwardly expanding depressions in theside wall of the Through Silicon VIA hole) are generated in the sidewallof the Through Silicon VIA holes when Through Silicon VIA holes areformed so as to pass through the non-active area in which the pluralityof dummy actives are uniformly disposed.

FIG. 1A is a plan view showing the surface structure of a semiconductorsubstrate in the Through Silicon VIA electrode formation area in aconventional image sensor. The Through Silicon VIA hole 21 has asubstantially cylindrical shape and is formed in the non-active area 100in which photodiodes, transistors and other active elements are notformed. The non-active area 100 comprises an STI region mainly composedof SiO₂. A plurality of island-shaped dummy actives 200 for preventingdishing is uniformed disposed in the non-active area (STI region). TheThrough Silicon VIA hole 21 is formed so as to pass through thenon-active area in which the plurality of dummy actives 200 is arrayed.At this point, dummy actives 200 are present in positions in which theouter edge of the Through Silicon VIA hole 21 passes because the arraypitch and the dimensions of the dummy actives 200 are relatively smallin comparison with the size of the Through Silicon VIA hole 21.

FIG. 1B is a cross-sectional view along the line 1B-1B in FIG. 1A. Aninterlayer insulating film 12 is formed on the semiconductor substrate10. The electrode pad 13 electrically connected to the sensor section isformed in the interlayer insulating film 12. The Through Silicon VIAelectrode is formed by forming a Through Silicon VIA hole 21 from thereverse surface of the semiconductor substrate toward the electrode pad13 by dry etching. Notches 300 are generated in the dry etching processwhen dummy actives 200 are present in positions through which the outeredge of the Through Silicon VIA hole passes, i.e., when the outer edgeof the Through Silicon VIA hole intersects with the dummy actives 200.The notches 300 are depressions formed in the sidewall of the ThroughSilicon VIA hole 21 in positions at the depth near the boundary betweenthe interlayer insulating film 12 and the semiconductor substrate 10. InFIG. 1A, the locations where notches are generated are indicated byshading. It is apparent from the drawing that the notches 300 aregenerated only in locations where the outer edge of the Through SiliconVIA hole 21 intersects with the dummy actives 200.

In the step for forming a Through Silicon VIA electrode, a ThroughSilicon VIA hole 21 is formed, after which a process is carried out tosequentially form plating composed of a barrier metal, a plating seedlayer, and electroconductive wiring of the Through Silicon VIA electrodeon the inner wall of the Through Silicon VIA hole. Cu is generally usedas the plating. However, because Cu is a typical material thatconstitutes metal contamination in the silicon device and diffuses intothe silicon substrate and the interlayer insulating film at lowertemperatures, there is a risk of a deterioration of the deviceperformance and reliability, for example, junction leaks and dielectricbreakdowns in the interlayer insulating film. For this reason, a barriermetal composed of Ti, Ti/Ni, or the like is formed between thesemiconductor substrate and the Cu film that constitutes theelectroconductive wiring of the Through Silicon VIA electrode in orderto prevent Cu-diffusion into the silicon substrate.

However, it is difficult to form a sufficient barrier metal in the areawhere notches are generated in the case that notches occur in thesidewall of the Through Silicon VIA hole, and insufficient coverage bythe barrier metal is liable to occur in notched area. In this case, Cucould diffuse into the semiconductor substrate in the areas where thereis insufficient coverage by the barrier metal, and the deviceperformance and reliability are seriously affected.

SUMMARY OF THE INVENTION

The present invention has been contrived in view of the above-describedissues, and an object is to provide a semiconductor device having anon-active area in which a dummy pattern is formed on the semiconductorsubstrate and a Through Silicon VIA electrode is formed so as to passthrough the non-active area, wherein the quality, reliability, andstability of the semiconductor device is improved by preventing theoccurrence of notches that are generated in a side wall of the ThroughSilicon VIA electrode.

The semiconductor device of the present invention is a semiconductordevice that comprises a semiconductor substrate having an active area inwhich a plurality of active elements are formed, and a non-active areaexcepting the active area; at least one electrode pad electricallyconnected to any of the active elements; and at least one ThroughSilicon VIA electrode electrically connected to the electrode pad by wayof the non-active area, wherein the non-active area has an insulatingregion obtained by forming an insulating film on the semiconductorsubstrate, and a dummy section obtained by leaving a base material ofthe semiconductor substrate in the insulating region, and an outer edgeof the Through Silicon VIA electrode does not intersect with theboundary between the insulating region and the dummy section.

The method for manufacturing a semiconductor device of the presentinvention is method for manufacturing a semiconductor device thatcomprises a step for forming, on a semiconductor substrate, an activearea in which a plurality of active elements are formed, and anon-active area excepting the active area; a step for forming at leastone electrode pad electrically connected to any of the active elements;and a step for forming at least one Through Silicon VIA electrodeelectrically connected to the electrode pad by way of the non-activearea, wherein the step for forming the non-active area includes a stepfor forming a dummy section obtained by leaving a base material of thesemiconductor substrate in an insulating region composed of aninsulating film; and the Through Silicon VIA electrode is formed suchthat an outer edge of thereof does not intersect with the boundarybetween the insulating region and the dummy section.

The method for manufacturing a semiconductor package of the presentinvention is a method for manufacturing a semiconductor package thatincludes the semiconductor device described above, comprising a step forforming a Through Silicon VIA hole from the reverse surface of thesemiconductor substrate to the electrode pad in a Through Silicon VIAelectrode formation area of said semiconductor substrate; a step forforming an insulating film on an inner wall of the Through Silicon VIAhole and the reverse surface of the semiconductor substrate; a step forselectively removing the insulating film of the bottom surface of theThrough Silicon VIA hole and exposing the electrode pad inside theThrough Silicon VIA hole; a step for sequentially forming a barriermetal and an electroconductive film for covering the reverse surface ofthe semiconductor substrate and the inner wall of the Through SiliconVIA hole to form the Through Silicon VIA electrode and reverse surfacewiring electrically connected to said Through Silicon VIA electrode onthe reverse surface of the semiconductor substrate; a step for formingan insulating film having an aperture on the reverse surface of thesemiconductor substrate; and a step for forming an external terminal onthe exposed portion of the reverse surface wiring through the aperture.

In accordance with the semiconductor device and the method formanufacturing a semiconductor device of the present invention, dishingof the STI region can be prevented by a dummy pattern formed in thenon-active area. The Through Silicon VIA electrode formation area of thenon-active area has a dummy pattern formed so that no area is generatedwherein the outer edge of the Through Silicon VIA electrode intersectsthe dummy section. Therefore, etching ions are not scattered in thevicinity of the sidewall of the Through Silicon VIA hole and theoccurrence of notches in the sidewall of the Through Silicon VIA holecan be prevented. Accordingly, a barrier metal can be formed on thesidewall of the Through Silicon VIA hole without the occurrence ofinsufficient coverage, and the diffusion of Cu constituting the platingas well as other impurities into the semiconductor substrate can bereliably prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view showing the configuration of a conventional dummypattern formed in a non-active area;

FIG. 1B is a cross-sectional view along the line 1B-1B in FIG. 1A;

FIG. 2 is a cross-sectional view of an image sensor according to anembodiment of the present invention;

FIG. 3 is a plan view showing the configuration of the reverse surfaceof the image sensor according to an embodiment of the present invention;

FIG. 4A is a plan view showing the configuration of the dummy pattern inthe Through Silicon VIA electrode formation area according to anembodiment of the present invention;

FIG. 4B is a cross-sectional view along the line 4B-4B in FIG. 4A;

FIG. 5 is a plan view showing the configuration of the dummy pattern inthe Through Silicon VIA electrode formation area according to anotherembodiment of the present invention;

FIG. 6 is a plan view showing the configuration of the dummy pattern inthe Through Silicon VIA electrode formation area according to anotherembodiment of the present invention;

FIG. 7 is a plan view showing the configuration of the dummy pattern inthe Through Silicon VIA electrode formation area according to anotherembodiment of the present invention;

FIG. 8 is a plan view showing the configuration of the dummy pattern inthe Through Silicon VIA electrode formation area according to anotherembodiment of the present invention;

FIGS. 9A to 9D are cross-sectional views showing the steps formanufacturing an image sensor according to an embodiment of the presentinvention; and

FIGS. 10E to 10G are cross-sectional views showing the steps formanufacturing an image sensor according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The supposed mechanism by which notches are generated in the side wallof a Through Silicon VIA hole when a Through Silicon VIA electrode isformed through a non-active area in which a plurality of dummy activesare uniformly disposed will be described with reference to FIGS. 1A and1B before a description regarding embodiments of the present inventionis given.

Notches in the sidewall of a Through Silicon VIA hole are known to begenerated in the dry etching step of a semiconductor substrate when aThrough Silicon VIA hole is formed. In the dry etching step, an STIregion 11 composed of SiO₂ is not etched by selective etching in thestep for etching silicon as the base material of a semiconductorsubstrate 10. For this reason, the inventor posits that etching ionsemitted by an etching device are reflected in the STI region 11, arescattered in the lateral direction, and collide with the sidewall of theThrough Silicon VIA hole 21, whereby the sidewall of the Through SiliconVIA hole is etched and notches 300 are generated. In other words, it isthought that when a boundary between the SIT region and the dummyactives 200 is present in the vicinity of the sidewall of the ThroughSilicon VIA hole 21, etching ions scattered at the boundary collide in ahigh-energy state with the sidewall of the Through Silicon VIA hole andform notches.

Embodiments of the present invention described below are improvements onthe configuration of a dummy pattern of a non-active area in the ThroughSilicon VIA electrode formation area, in that a dummy pattern isprovided in such a way as to avoid the formation of an area in which theouter edge of the Through Silicon VIA hole intersects the boundarybetween the dummy section and the STI region. Therefore, a boundarybetween the dummy section and the STI region, which causes the etchingions to be scattered, is not formed in the vicinity of the sidewall ofthe Through Silicon VIA hole. Embodiments of the present invention aredescribed below with reference to the drawings.

FIG. 2 is a cross-sectional view of an image sensor according to anembodiment of the present invention. A semiconductor substrate 10composed of a single-crystal silicon or the like constitutes the mainbody of the image sensor, and formed on the substrate are transistorsand other active elements 30 constituting a photodiode and peripheralcircuits for processing signals that have undergone photoelectricexchange in the photodiode. Light receiving elements are formed on thesemiconductor substrate 10 in a number commensurate with the number ofpixels, and the light emitted from an imaging target is formed as animage on the surface of the light receiving elements by externallyprovided lenses or another optical system. Each of the light receivingelements outputs a photoelectric conversion signal that corresponds tothe intensity of the received light, as a detected output signal Imagedata is generated from the position of each light receiving element andthe detected output signals.

An interlayer insulating film 12 composed of SiO₂ or the like is formedon the surface of the semiconductor substrate 10. Electroconductivewiring 14 having a multilayer structure electrically connected to theactive elements 30 is formed inside the interlayer insulating film 12.An electrode pad 13 that is electrically connected to theelectroconductive wiring 14 is provided in the region further outsidethe region in which the active elements 30 constituting the sensorsection are formed. A color filter 15 for separating the received lightinto three primary colors is provided on the surface of the interlayerinsulating film 12. A cover glass 17 is mounted on the interlayerinsulating film 12 via an adhesive sheet 16.

A Through Silicon VIA electrode 20 is provided in the semiconductorsubstrate 10, from the reverse surface of the semiconductor substrate tothe electrode pad 13 inside the interlayer insulating film 12. TheThrough Silicon VIA electrode 20 is formed by sequentially forming onthe bottom surface and sidewall of the Through Silicon VIA hole abarrier metal 22 composed of Ti, Ti/Ni, or the like, a plating seed film23 composed of Cu or the like and, and a plating film 24 composed of Cuor the like. These electroconductive films constituting the ThroughSilicon VIA electrode 20 are connected to the electrode pad 13 on thebottom surface of the Through Silicon VIA hole, and are connected to thereverse surface wiring 25 that extends to the reverse surface of thesemiconductor substrate 10. The insulation between electroconductivefilm of the Through Silicon VIA electrode 20 or reverse surface wiring25 and the semiconductor substrate 10 is ensured by the insulating film18 composed of SiO₂ or the like formed along the sidewall of the ThroughSilicon VIA hole and the reverse surface of the semiconductor substrate10. A solder resist 40 is formed on the reverse surface of thesemiconductor substrate 10 so as to embed the Through Silicon VIA holeof the Through Silicon VIA electrode 20. An aperture is formed in thesolder resist 40. A revere surface electrode pad that constitutes aportion of the reverse surface wiring 25 is provided in the exposedportion through the aperture. A solder bump 41 is provided on thereverse surface electrode pad, thereby constituting an externalconnection terminal electrically connected to the electrode pad 13 viathe Through Silicon VIA electrode 20 and the reverse surface wiring 25.In this manner, the package of the image sensor of the presentembodiment has a W-CSP configuration, which is the same size as thesemiconductor substrate 10.

FIG. 3 is a plan view of the image sensor of the present embodiment asseen from the reverse surface side of the semiconductor substrate 10. Inthe drawing, a plurality of Through Silicon VIA electrodes 20 is formedalong the outer edge of the semiconductor substrate 10. The solder bumps41 are arranged in the form of a grid on the reverse surface of thesemiconductor substrate 10 and are electrically connected to thecorresponding Through Silicon VIA electrodes 20 via the reverse surfacewiring 25. The region enclosed by the broken line in the drawing is aregion for forming a sensor circuit in which photodiodes, transistors,and other active elements are formed. Each of the Through Silicon VIAelectrodes 20 is formed in areas that correspond to the non-active areain which active elements are not formed.

FIG. 4A is a plan view showing the surface structure of thesemiconductor substrate 10 in the formation area of the Through SiliconVIA electrode 20. The formation area of the Through Silicon VIAelectrode 20 is clearly shown in the drawing. The Through Silicon VIAhole 21 of the Through Silicon VIA electrode having a substantiallycylindrical shape is formed in the non-active area 100 in whichphotodiodes and other active elements are not formed. The STI region 11formed by embedding SiO₂ film in a trench formed in the surface of thesemiconductor substrate 10 extends across the entire surface of thenon-active area 100. Since the STI region 11 formed in the non-activearea 100 has a relatively large surface area, there is a concern thatdishing will occur in the CMP step that is carried out when the STIregion 11 is formed. Therefore, a dummy pattern is formed in thenon-active area 100 in order to prevent dishing. The dummy pattern isprovided by disposing a plurality of island-shaped dummy actives 200 inthe non-active area 100. The dummy actives 200 are formed by partiallyexposing the silicon in the SiO₂ film constituting the STI region.Therefore, active elements can be formed on the dummy actives, and sincethe dummy actives are formed exclusively for the purpose of preventingdishing and do not contribute any function to the image sensor,transistors and other active elements do not need to be formed on thedummy actives. However, in the present invention, active elements may beformed on the dummy actives. In other words, a gate electrode and drainand source regions may be formed on the dummy actives, but these willnot contribute function to the image sensor and electrodes and regionshaving functionality as a dummy pattern are essentially included in thedummy actives. In this case, the active elements formed on the dummyactives must be isolated from the main circuit so that they do notoperate.

In the present embodiment, the dummy actives 200 are not formed in theregion that overlaps the Through Silicon VIA electrode 20. In otherwords, the dummy actives 200 are formed only in the region outside theThrough Silicon VIA electrode formation area and are not formed insidethe Through Silicon VIA electrode formation area.

FIG. 4B is a cross-sectional view along the line 4B-4B in FIG. 4A. Asdescribed above, the dummy actives 200 are not present inside theThrough Silicon VIA electrode formation area, the Through Silicon VIAhole 21 is formed in the region in which only the SiO₂ film constitutingthe STI region 11 is present, and there is no portion in which the outeredge of the Through Silicon VIA electrode 20 intersects with theboundary between the STI region and the dummy actives. Therefore, theboundary between the STI region and the dummy actives where etching ionsare scattered is not present in the vicinity of the sidewall of theThrough Silicon VIA hole 21. The lateral scattering of the etching ionscan be completely prevented in the dry etching step for forming theThrough Silicon VIA hole 21. Therefore, the generation of notches in thesidewall of the Through Silicon VIA hole 21 can be effectivelyprevented. Since the barrier metal 22 can be formed without theoccurrence of insufficient coverage on the sidewall of the ThroughSilicon VIA hole 21, the diffusion of Cu constituting the plating film24 into the semiconductor substrate can be prevented.

FIG. 5 is a plan view showing the surface structure of the semiconductorsubstrate 10 in the Through Silicon VIA electrode formation area of thesemiconductor device according to a second embodiment of the presentinvention. The formation area of the Through Silicon VIA electrode 20 isclearly shown in the drawing. In the present embodiment, dummy activesare not formed in the region that overlaps the Through Silicon VIAelectrode formation area in the same manner as the first embodimentdescribed above. In the present embodiment, a rectangular ring-shapeddummy active 201 that surrounds the Through Silicon VIA electrodeformation area is additionally provided. In other words, a formationarea for the Through Silicon VIA electrode 20 is arranged in an STIregion 11 a extending inside of the rectangular ring-shaped dummy active201 wherein dummy actives are not formed. The STI region 11 in which aplurality of island-shaped dummy actives 200 are uniformly disposedextends around the periphery of the rectangular ring-shaped dummy active201. There is no portion in which the outer edge of the Through SiliconVIA electrode 20 intersects with the boundary between the STI region andthe dummy actives even in the case that the non-active area 100 in theThrough Silicon VIA electrode formation area has such a structure. Inthe same manner as the first embodiment, the lateral scattering ofetching ions can be completely prevented in the dry etching step forforming the Through Silicon VIA hole 21. Accordingly, the generation ofnotches in the sidewall of the Through Silicon VIA hole 21 can beeffectively prevented. Since the barrier metal 22 can be formed withoutthe occurrence of insufficient coverage on the sidewall of the ThroughSilicon VIA hole 21, the diffusion of Cu constituting the plating film24 into the semiconductor substrate can be prevented. In the presentembodiment, the anti-dishing effect can be improved by providing arectangular ring-shaped dummy active 201 around the outer periphery ofthe Through Silicon VIA electrode formation area. In other words, sincedummy actives are not disposed in the Through Silicon VIA electrodeformation area, the surface area of the portion composed only of the STIregion is increased, resulting in a structure that is liable to undergodishing in the portion. However, the effect of preventing dishing isgreater than that of the first embodiment because the density of thedummy actives is increased at the periphery of the Through Silicon VIAelectrode formation area by surrounding the Through Silicon VIAelectrode formation area with the rectangular ring-shaped dummy active201. The external shape of the rectangular ring-shaped dummy active 201is not limited to a rectangular shape, and, e.g., a polygonal shapeother than a quadrangular shape, a circular shape, or any shape thatfollows the outer edge of the Through Silicon VIA hole 21 may be used.

FIG. 6 is a plan view showing the surface structure of the semiconductorsubstrate 10 in the Through Silicon VIA electrode formation area of thesemiconductor device according to a third embodiment of the presentinvention. The formation area of the Through Silicon VIA electrode 20 isclearly shown in the drawing. As shown in the drawing, a plurality ofisland-shaped dummy actives 202 are formed in the Through Silicon VIAelectrode formation area in the present embodiment, which is differentfrom the first embodiment (FIG. 4A) described above. Dummy actives arenot arranged in a position through which the outer edge of the ThroughSilicon VIA hole 21 passes. Dummy actives are disposed in the regionsoutside and in the center of the Through Silicon VIA electrode formationarea. In view of the fact that notches occur only in portions in whichthe outer edge of the Through Silicon VIA hole 21 pass through dummyactives, as shown in FIG. 1A, it is thought that there is substantiallyno effect of scattered etching ions when the dummy actives are notdisposed on the outer edge of the Through Silicon VIA hole 21.Therefore, dummy actives 202 can be formed inside of the Through SiliconVIA electrode formation area in a range that is not affected bylaterally scattered etching ions. There are no portions in which theouter edge of the Through Silicon VIA electrode 20 intersects with theboundary between the STI region and the dummy actives even in the casethat the non-active area 100 in the Through Silicon VIA electrodeformation area has such a structure. On the other hand, dummy actives202 are present in the Through Silicon VIA electrode formation area, andbecause of this, etching ions are scattered in the boundary between theSTI region and the dummy actives 202. However, since an adequatedistance to the sidewall of the Through Silicon VIA hole 21 is assured,it is expected that a possibility that the scattered etching ions etchthe sidewalls of the Through Silicon VIA hole 21 and notches aregenerated lowers. Therefore, the diffusion of Cu constituting theplating film into the semiconductor substrate can be prevented becausethe barrier metal can be formed without the occurrence of insufficientcoverage on the sidewall of the Through Silicon VIA hole 21. The effectof preventing dishing is greater than that of the first embodimentdescribed above because the density of the dummy actives around theperiphery of the Through Silicon VIA electrode formation area is madegreater by providing dummy actives 202 inside of the Through Silicon VIAelectrode formation area.

FIG. 7 is a plan view showing the surface structure of the semiconductorsubstrate 10 in the Through Silicon VIA electrode formation area of thesemiconductor device according to a fourth embodiment of the presentinvention. The formation area of the Through Silicon VIA hole 21 isclearly shown in the drawing. As shown in the drawing, a rectangulardummy active 203 having a larger surface area than the surface area ofthe aperture of the Through Silicon VIA hole 21 is disposed in theThrough Silicon VIA electrode formation area. The STI region 11 in whicha plurality of island-shaped dummy actives 200 are uniformly disposedextends around the periphery of the rectangular dummy active 203. Thereare no portions in which the outer edge of the Through Silicon VIAelectrode 20 intersects with the boundary between the STI region and thedummy actives even in the case that the non-active area 100 in theThrough Silicon VIA electrode formation area has such a structure.Therefore, the lateral scattering of etching ions can be completelyprevented in the dry etching step for forming the Through Silicon VIAhole 21. Accordingly, the generation of notches in the sidewall of theThrough Silicon VIA hole 21 can be effectively prevented. Since thebarrier metal can be formed without the occurrence of insufficientcoverage on the sidewall of the Through Silicon VIA hole 21, thediffusion of Cu constituting the plating film 24 into the semiconductorsubstrate can be prevented. The effect of preventing dishing is greaterthan that of the first embodiment described above because the density ofthe dummy actives around the periphery of the Through Silicon VIAelectrode formation area is made greater by providing a dummy active 203having a relatively large surface area in the Through Silicon VIAelectrode formation area. In the present embodiment the external shapeof the dummy active 203 is rectangular, but no limitation is imposedthereby, and other polygonal shapes, a circular shape, or any shape thatfollows the outer edge of the Through Silicon VIA hole 21 may be used.

FIG. 8 is a plan view showing the surface structure of the semiconductorsubstrate 10 in the Through Silicon VIA electrode formation area of thesemiconductor device according to a fifth embodiment of the presentinvention. The formation area of the Through Silicon VIA electrode isclearly shown in the drawing. A rectangular ring-shaped dummy active 204is formed so as to surround an STI region 11 b provided inside theThrough Silicon VIA electrode formation area and so as to occupy aregion having a fixed range that includes the outer edge of the ThroughSilicon VIA electrode 20. A plurality of island-shaped dummy actives 205is disposed in the STI region 11 b. The STI region 11 in which aplurality of island-shaped dummy actives 200 is uniformly disposedextends around the periphery of the rectangular ring-shaped dummy active204. There is no portion in which the outer edge of the Through SiliconVIA electrode 20 intersects with the boundary between the STI region andthe dummy actives even in the case that the non-active area 100 in theThrough Silicon VIA electrode formation area has such a structure.Provided that an adequate distance from the boundary between the dummyactive 204 and the STI region 11 b to the sidewall of the ThroughSilicon VIA hole 21 is assured, then even when etching ions arescattered in the boundary, there is little possibility that notches willbe generated when the scattered etching ions etch the sidewalls of theThrough Silicon VIA hole 21. Therefore, the diffusion of the platingfilm into the semiconductor substrate can reliably be prevented becausethe barrier metal can be formed without the occurrence of insufficientcoverage on the sidewall of the Through Silicon VIA hole 21. The effectof preventing dishing is greater than that of the first embodimentdescribed above because the density of the dummy actives around theperiphery of the Through Silicon VIA electrode formation area is madegreater by providing dummy actives 204 and 205 in the Through SiliconVIA electrode formation area.

Described next with reference to FIGS. 9A to 9D and FIGS. 10E to 10G isa method for manufacturing a package of an image sensor using asemiconductor device having the structure described in the embodimentsabove.

First, a wafer is prepared having a semiconductor substrate 10 on whichare formed active elements 30 composed of photodiodes, cell amplifiers,and other sensor sections, color filters 15, electrode pads 13, and thelike. A dummy pattern having a configuration shown in the embodimentsdescribed above is formed (FIG. 9A) in the non-active area including theThrough Silicon VIA electrode formation area of the semiconductorsubstrate 10.

Meanwhile, a cover glass 17 is prepared in which a protective film 19has been affixed to the surface. The protective film 19 is provided forprotecting the cover glass 17 from damage during the manufacturing stepsand is affixed so as to cover the entire upper surface of the coverglass 17. The cover glass 17 is then affixed to the light receivingelements formation surface of the semiconductor substrate 10 via anadhesive sheet 16 (FIG. 9B).

Next, the reverse surface of the semiconductor substrate 10 is polisheduntil the thickness of the semiconductor substrate 10 reaches apredetermined value (FIG. 9C).

A photoresist having an aperture in the portion that corresponds to theThrough Silicon VIA electrode formation area is subsequently formed onthe reverse surface of the semiconductor substrate 10. The semiconductorsubstrate 10 exposed through the aperture of the photoresist isdry-etched from the reverse surface side to form a Through Silicon VIAhole 21 that reaches the electrode pad 13 inside the interlayerinsulating film 12 (FIG. 9D). The Through Silicon VIA hole 21 is formedin the non-active area in which the dummy pattern corresponding to theembodiments described above is formed. In other words, the boundarybetween the dummy actives and the STI region is not present in thevicinity of the sidewall of the Through Silicon VIA hole 21 and etchingions are not scattered in the lateral direction. Therefore, notches arenot generated in the sidewall of the Through Silicon VIA hole 21.

Next, an insulating film 18 composed of SiO₂ film is deposited by CVDmethod so as to cover the reverse surface of the semiconductor substrate10 and the inner wall of the Through Silicon VIA hole 21. The insulatingfilm 18 deposited on the bottom surface of the Through Silicon VIA hole21 is etched to exposed the electrode pad 13 inside the Through SiliconVIA hole 21 (FIG. 10E).

Next, a barrier metal 22 composed of Ti, Ti/Ni, or the like and aplating seed film 23 composed of Cu are sequentially formed on thesidewall and bottom surface of the Through Silicon VIA hole 21 as wellas the reverse surface of the semiconductor substrate 10 by sputteringmethod. Because notches have not been generated in the sidewall of theThrough Silicon VIA hole 21, the barrier metal can therefore be formedwithout the occurrence of insufficient coverage. Next, an electrode isconnected to the plating seed film 23 and a plating film 24 composed ofCu is formed on the inner wall of the Through Silicon VIA hole 21 byelectroplating method, thereby forming a Through Silicon VIA electrode20. Reverse surface wiring 25 is then formed on the reverse surface ofthe semiconductor substrate 10. A resist is thereafter formed on thereverse surface of the semiconductor substrate 10 on which Cu film isformed using a photosensitive dry film or the like. The reverse surfacewiring 25 is formed by etching Cu film through the resist. The ThroughSilicon VIA electrode 20 is electrically connected to the electrode pad13 on the bottom surface of the Through Silicon VIA hole 21. The reversesurface wiring 25 is electrically connected to the electrode pad 13 viathe Through Silicon VIA electrode 20 (FIG. 10F).

Next, a solder resist 40 as an insulating film composed of aphotosetting epoxy resin is coated so as to cover the entire reversesurface of the semiconductor substrate 10 on which the reverse surfacewiring 25 is formed. The solder resist 40 is dehydrated and then theexposed portions of the solder resist 40 through a photoresist arephoto-cured. The interior of the Through Silicon VIA hole 21 is filledwith the solder resist 40. Unexposed portions of the solder resist 40are selectively removed to form apertures in the solder bump formationregion. Next, a solder bump 41 is formed in the pad area of the reversesurface wiring 25 exposed through the aperture of the solder resist 40by electroplating method or the like (FIG. 10G).

Next, the protective film 19 affixed to the cover glass 17 is peeledaway, the cover glass is affixed to a wafer tape, and an image sensor isformed into a chip shape through the dicing process. The image sensorpackage is completed by carrying out the steps described above.

According to the semiconductor device and the method for manufacturing asemiconductor device of the present invention, it is obvious from thedescription above that dishing in the STI region can be prevented byusing a dummy pattern formed in the non-active area. Dummy actives aredisposed in the Through Silicon VIA electrode formation area of thenon-active area such that there are no portions in which the outer edgeof the Through Silicon VIA electrode intersects with the dummy actives;i.e., there are no portions in which the STI region and the dummyactives are adjacent in the vicinity of the sidewall of the ThroughSilicon VIA hole. Therefore, etching ions are not scattered in thevicinity of the sidewall of the Through Silicon VIA hole, and theoccurrence of notches in the sidewall of the Through Silicon VIA holecan be prevented. A barrier metal can be formed on the sidewall of theThrough Silicon VIA hole without the occurrence of insufficientcoverage, and the diffusion of Cu and other impurities constituting theplating film into the semiconductor substrate can be reliably prevented.

The present invention has been described above with reference to thepreferred embodiments. It is apparent that various modifications andchanges can be envisioned by persons skilled in the art. All suchmodifications and changes are understood be included within the range ofthe appended claims.

What is claimed is:
 1. A method for manufacturing a semiconductordevice, comprising: a step for forming, on a semiconductor substrate, anactive area in which a plurality of active elements are formed, and anon-active area excepting said active area; a step for forming at leastone electrode pad electrically connected to any of said active elements;and a step for forming at least one Through Silicon VIA electrodeelectrically connected to said electrode pad by way of said non-activearea, wherein the step for forming said non-active area includes a stepfor forming a dummy section obtained by leaving a base material of saidsemiconductor substrate in an insulating region composed of aninsulating film; and said Through Silicon VIA electrode is formed suchthat an outer edge of thereof does not intersect with the boundarybetween said insulating region and said dummy section.
 2. The method formanufacturing a semiconductor device of claim 1, wherein the step forforming said non-active area includes a step for providing said dummysection in only the outside of the region through which said ThroughSilicon VIA electrode passes.
 3. The method for manufacturing asemiconductor device of claim 1, further comprising a step for providinga ring-shaped dummy section for surrounding the region through whichsaid Through Silicon VIA electrode passes.
 4. The method formanufacturing a semiconductor device of claim 1, wherein the step forforming said non-active area includes a step for providing said dummysection outside and inside the region through which said Through SiliconVIA electrode passes.
 5. The method for manufacturing a semiconductordevice of claim 1, wherein the step for forming said non-active areaincludes a step for forming a dummy section that extends over the entiresurface of the region through which said Through Silicon VIA electrodepasses.